Old Questions on Diploma Electronics Engineering

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Old Questions on Diploma Electronics Engineering

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Diploma Electronics Engineering Old Questions Paper

1. A CE amplifier has re=6Ω, β=100. The input impedance is
(a) 6Ω
(b) 98Ω
(c) 100Ω
(d) 600Ω

2. The most commonly used bias in BJT amplifier circuit is
(a) voltage divider bias
(b) emitter bias
(c) collector bias
(d) collector feedback bias

3. In a commercially available good power supply the voltage regulation is about
(a) 1%
(b) 5%
(c) 10%
(d) 20%

4. A voltage doubler circuit uses
(a) two diodes
(b) two capacitors
(c) two diodes and two capacitors
(d) none of these

5. Slew rate of an ideal OP-Amp is
(a) Zero
(b) 1V/μs
(c) 10V/μs
(d) ∞

6. If an OP-Amp has unity gain frequency of 1MHz, the cut off frequency at gain 10 will be
(a) 100KHz
(b) 1MHz
(c) 10MHz
(d) 90MHz

7. A Darlington pair is used for
(a) low distortion
(b) high bandwidth
(c) high power gain
(d) high current gain

8. An ideal OP-Amp has
(a) infinite input and output impedance
(b) low input and output impedance
(c) low input and high output impedance
(d) infinite input and zero output impedance

9. Which of the following OP-Amp circuits has zero resistance in the feedback path?
(a) inverting amplifier
(b) non-inverting amplifier
(c) source follower
(d) summing amplifier

10. An OP-Amp has zero gain for common mode inputs. The CMRR is
(a) Zero
(b) High
(c) Infinite
(d) low

11. Which OP-Amp circuit uses a resistance in series with input and capacitor in feedback path?
(a) differentiating amplifier
(b) integrator
(c) logarithmic amplifier
(d) exponential amplifier

12. In which of the following circuit is OP-Amp used in open loop configuration?
(a) comparator
(b) Summing amplifier
(c) Integrator
(d) multiplier

13. In which amplifier circuit is gate conductance negligible?
(a) JFET
(c) Both (a) and (b)
(d) None of these

14. Which of the following parameters has the unit of ohms?
(a) hie
(b) hre
(c) hfe
(d) hoe

15. A virtual ground is a ground for
(a) voltage
(b) current
(c) both (a) & (b)
(d) none of these

16. In an op-Amp common mode signal is applied to
(a) inverting terminal
(b) non-inverting terminal
(c) both terminals
(d) one or both terminals

17. A negative feedback can be of
(a) only one type
(b) 2 types
(c) 3 types
(d) 4 types

18. Which of the following binary numbers is equivalent to decimal 10?
(a) 1000
(b) 1001
(c) 1010
(d) 1100

19. Which of these are two state devices?
(a) Lamp
(b) punched card
(c) magnetic tape
(d) all of above

20. Logic analyzer is
(a) multi channel oscilloscope
(b) similar to logic pulser
(c) similar to current tracer
(d) none of the above

21. Binary number 1101 is equal to which octal number given below?
(a) 13
(b) 14
(c) 15
(d) 17

22. In a 4 input AND gate, the total numbers of high outputs for 16 input states are
(a) 16
(b) 8
(c) 4
(d) 1

23. Which of these are universal gates?
(a) Only NOR
(b) Only NAND
(c) NOR and NAND

24. The number of NOT gates present in a 14 pin NOT gate IC is
(a) 8
(b) 6
(c) 5
(d) 4

25. Which of the following is true?
(a) SOP is two level logic
(b) POS is two level logic
(c) Both SOP and POS are two level logic
(d) Hybrid function is two level logic

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26. In which function is each term known as minterm?
(a) SOP
(b) POS
(c) Hybrid
(d) Both SOP and POS

27. In the expression (A+BC), the total number of minterms will be
(a) 2
(b) 3
(c) 4
(d) 5

28. In a four variable Karnaugh map eight adjacent cells gives a
(a) two variable term
(b) single variable term
(c) three variable term
(d) four variable term

29. As compared to TTL, ECL has
(a) lower power dissipation
(b) lower propagation delay
(c) higher noise margin
(d) higher propagation delay

30. TSL inverter has
(a) one input
(b) two inputs
(c) three inputs
(d) none of these

31. A 3 bit binary adder should use
(a) 3 full adders
(b) 2 full adders and one half adder
(c) 1 full adder and two half adders
(d) 3 half adders

32. BCD input 1000 is fed to a 7-segment display through a BCD to 7-segment detector. The segments which will light up are
(a) a, b, d
(b) a, b, c
(c) a, b, g, e, d
(d) all segments

33. How many data select lines are required in a 8:1 multiplexer?
(a) 1
(b) 2
(c) 3
(d) 4

34. It is desired to route data from many resisters to one resister. The device needed is
(a) Decoder
(b) Multiplexer
(c) Demultiplexer
(d) counter

35. In a positive edge triggered JK Flip Flop, J=1, K=0 and clock pulse is rising. Q will be
(a) 0
(b) 1
(c) no change
(d) toggle

36. A counter has a modulus of 10. The number of Flip Flops used is
(a) 10
(b) 5
(c) 4
(d) 3

37. A counter has 4 Flip Flops. It divides the input frequency by
(a) 16
(b) 8
(c) 4
(d) 2

38. A 4 bit down counter can count from
(a) 0000 to 1111
(b) 1111 to 0000
(c) 000 to 111
(d) 111 to 000

39. In a shift register, shifting left by one bit means
(a) division by 2
(b) multiplication by 2
(c) subtraction by 2
(d) any of the above

40. Quantization error occurs in
(a) D/A converter
(b) A/D converter
(c) both (a) and (b)
(d) neither (a) nor (b)

41. Which of the following is error correcting code?
(c) Hamming
(d) Gray

42. A parity detector can detect
(a) single error only
(b) single or odd number of errors
(c) two errors only
(d) even number of errors

43. Which of the following contains an organic fluid?
(a) LED
(b) LCD
(c) LED and LCD
(d) none of these

44. Which of them has 10 inputs and 4 outputs?
(a) Decimal to BCD encoder
(b) BCD to decimal decoder
(c) Octal to binary encoder
(d) All encoders

45. Which of the following is equivalent to AND-OR realization?

46. The number of memory locations which 14 address bits can access is
(a) 1024
(b) 2048
(c) 4096
(d) 16384

47. State transition table and state transition diagram form part of design steps for
(a) combinational circuits
(b) sequential circuits
(c) delay circuits
(d) all of the above

48. In digital circuits Schottky transistors are preferred over normal transistors because of their
(a) low propagation delay
(b) lower power dissipation
(c) higher propagation delay
(d) higher power dissipation

49. A transistor is used as non-saturated switch to eliminate
(a) turn on time
(b) turn off time
(c) storage time
(d) delay time

50. The initial state of a MOD-16 counter is 0110. After 37 clock pulses the state of the counter will be
(a) 1011
(b) 0110
(c) 0101
(d) 0001