Important Questions on Computer Science and Engineering

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Important Questions on Computer Science and Engineering
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Computer Science and Engineering Important Question Paper

1. Which of the following statements apply to CMOS devices?
(a) The devices should not be inserted into circuits with the power on.
(b) All tools, test equipment, and metal workbenches should be tied to earth ground.
(c) The devices should be stored and shipped in antistatic tubes or conductive foam.
(d) All of these

2. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains __________.
(a) 0000
(b) 1111
(c) 0111
(d) 1000

3. A BCD counter is a __________.
(a) binary counter
(b) full-modulus counter
(c) decade counter
(d) divide-by-10 counter

4. If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured at:
(a) Source of the both transistor
(b) Drains of the both transistor
(c) Drain of n-MOS and source of p-MOS
(d) Source of n-MOS and drain of p-MOS

5. Which of the following is a type of error associated with digital-to-analog converters (DACs)?
(a) nonmonotonic error
(b) incorrect output codes
(c) offset error
(d) nonmonotonic and offset error

6. In a comparator, if we get input as A>B then the output will be
(a) 1
(b) 0
(c) A
(d) B

7. The base emitter voltage in a cut off region of silicon transistor is__________
(a) greater than 0.7V
(b) equal to 0.7V
(c) less than 0.7V
(d) cannot be predicted

8. The switching of power with a PNP transistor is called__________
(a) sourcing current
(b) sinking current
(c) forward sourcing
(d) reverse sinking

9. The collector current will not reach the steady state value instantaneously because of__________
(a) stray capacitances
(b) resistances
(c) input blocking capacitances
(d) coupling capacitance

10. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
(a) 2, 2
(b) 2, 3
(c) 3, 3
(d) None of these

11. DeMorgan’s theorem states that
(a) (AB)’ = A’ + B’
(b) (A + B)’ = A’ * B
(c) A’ + B’ = A’B’
(d) None of these

12. Simplify Y = AB’ + (A’ + B)C
(a) AB’ + C
(b) AB + AC
(c) A’B + AC’
(d) AB + A

13. Transistor–transistor logic (TTL) is a class of digital circuits built from
(a) Transistors only
(b) Bipolar junction transistors (BJT)
(c) Resistors
(d) Bipolar junction transistors (BJT) and resistors

14. The first machine cycle of an instruction is always
(a) A memory read cycle
(b) A fetch cycle
(c) An I/O read cycle
(d) A memory write cycle

15. A number of 1-bit registers used in microprocessors to indicate certain conditions are usually referred to as
(a) shift registers
(b) flags
(c) counters
(d) unit register

16. Which of the following buses is primarily used to carry signals that direct other Instructions to find out what type of operation is being performed?
(a) data bus
(b) control bus
(c) address bus
(d) address decoder bus

17. The performance of a pipelined processor suffers if
(a) the pipeline stages have different delays
(b) consecutive instructions are dependent on each other
(c) the pipeline stages share hardware resources
(d) all of these

18. How many address lines are needed to address each memory locations in a 2048×4 memory chip?
(a) 10
(b) 11
(c) 8
(d) 12

19. Memory access in RISC architecture is limited to instructions
(a) CALL and RET
(b) PUSH and POP
(c) STA and LDA
(d) MOV and JMP

20. Which memory has lowest access time?
(a) Registers
(b) Magnetic disk
(c) Main Memory
(d) Pen Drive

21. The minimum time delay between two successive memory read operations is __________.
(a) Cycle time
(b) Latency
(c) Delay
(d) None of these

22. A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
(a) 400
(b) 500
(c) 600
(d) 700

23. Which method/s of representation of numbers occupies large amount of memory than others?
(a) Sign-magnitude
(b) 1’s compliment
(c) 2’s compliment
(d) 1’s & 2’s compliment

24. How many bits are required to store one BCD digit?
(a) 1
(b) 2
(c) 3
(d) 4

25. The address space is 22 bits, the memory is 32 bit word addressable. What is the memory size?
(a) 16MB
(b) 512KB
(c) 4MB
(d) 1GB

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26. The ALU makes use of __________ to store the intermediate results.
(a) Accumulators
(b) Registers
(c) Heap
(d) Stack

27. __________ are numbers and encoded characters, generally used as operands.
(a) Input
(b) Data
(c) Information
(d) Stored Values

28. The I/O interface required to connect the I/O device to the bus consists of __________
(a) Address decoder and registers
(b) Control circuits
(c) Address decoder, registers and Control circuits
(d) Only Control circuits

29. The time delay between two successive initiation of memory operation __________
(a) Memory access time
(b) Memory search time
(c) Memory cycle time
(d) Instruction delay

30. The internal Components of the processor are connected by __________
(a) Processor intra-connectivity circuitry
(b) Processor bus
(c) Memory bus
(d) Rambus

31. __________ are used to over come the difference in data transfer speeds of various devices.
(a) Speed enhancing circuitory
(b) Bridge circuits
(c) Multiple Buses
(d) Buffer registers

32. The main advantage of multiple bus organisation over single bus is __________
(a) Reduction in the number of cycles for execution
(b) Increase in size of the registers
(c) Better Connectivity
(d) None of these

33. In case of Zero-address instruction method, the operands are stored in __________
(a) Registers
(b) Accumulators
(c) Push down stack
(d) Cache

34. The addressing mode which makes use of in-direction pointers is __________
(a) Indirect addressing mode
(b) Index addressing mode
(c) Relative addressing mode
(d) Offset addressing mode

35. Which method/s of representation of numbers occupies large amount of memory than others?
(a) Sign-magnitude
(b) 1’s compliment
(c) 2’s compliment
(d) 1’s & 2’s compliment

36. The pipelining process is also called as __________
(a) Superscalar operation
(b) Assembly line operation
(c) Von neumann cycle
(d) None of these

37. If a unit completes its task before the allotted time period, then
(a) It’ll perform some other task in the remaining time
(b) Its time gets reallocated to different task
(c) It’ll remain idle for the remaining time
(d) None of these

38. Which of the architecture is power efficient?
(a) CISC
(b) RISC
(c) ISA
(d) IANA

39. To access the services of operating system, the interface is provided by the:
(a) System calls
(b) API
(c) Library
(d) Assembly instructions

40. By operating system, the resource management can be done via:
(a) time division multiplexing
(b) space division multiplexing
(c) both time and space division multiplexing
(d) none of these

41. If a process fails, most operating system write the error information to a:
(a) log file
(b) another running process
(c) new file
(d) none of these

42. A process can be terminated due to:
(a) normal exit
(b) fatal error
(c) killed by another process
(d) all of these

43. The address of the next instruction to be executed by the current process is provided by the:
(a) CPU registers
(b) Program counter
(c) Process stack
(d) Pipe

44. What is a short-term scheduler?
(a) It selects which process has to be brought into the ready queue
(b) It selects which process has to be executed next and allocates CPU
(c) It selects which process to remove from memory by swapping
(d) None of these

45. In a time-sharing operating system, when the time slot given to a process is completed, the process goes from the running state to the:
(a) Blocked state
(b) Ready state
(c) Suspended state
(d) Terminated state

46. Suppose that a process is in “Blocked” state waiting for some I/O service. When the service is completed, it goes to the:
(a) Running state
(b) Ready state
(c) Suspended state
(d) Terminated state

47. Which one of the following is a synchronization tool?
(a) Thread
(b) Pipe
(c) semaphore
(d) socket

48. Mutual exclusion can be provided by the:
(a) mutex locks
(b) binary semaphores
(c) both mutex locks and binary semaphores
(d) none of these

49. To enable a process to wait within the monitor,
(a) a condition variable must be declared as condition
(b) condition variables must be used as boolean objects
(c) semaphore must be used
(d) all of these

50. Process are classified into different groups in:
(a) shortest job scheduling algorithm
(b) round robin scheduling algorithm
(c) priority scheduling algorithm
(d) multilevel queue scheduling algorithm